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308 публикаций

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What Went Wrong with Data Lakes? A 15-Year Reality Check from the Field
An AI Security Agent for University ACMIS: Multi-Vector Threat Detection and Automated Response
BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models
Extended Abstract: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0
KATANA: A Fast, Low-Power Mapping of Kalman Filters onto Edge NPUs for Real-Time Tracking
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference
Design of a Hardware-Efficient Hybrid FFT Processor Architecture for Real-Time Signal Processing Applications
Side-Channel Attacks Bypass Protection in 3D Printers
HARBOR: Heading Analysis and Reconstruction from Behavioral Observation and Radar
I'm Sorry Driver, I'm Afraid I Can't Do That: Appraising the Safety of LLMs within Automotive Contexts
TileFuse: A Fused Mixed-Precision Kernel Library for Efficient Quantized LLM Inference on AMD NPUs
HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
Modern analog computing for solving differential and matrix equations
Alignment Collapse Under KV Cache Quantization: Diagnosis and Mitigation
Microprogrammed CPU Design
QnRL: Quantum-Native Reinforcement Learning
xSense Design Cards: Guiding the Design of Multisensory Experiences
Feature Encoding in Quantum Machine Learning: A Survey and Practical Guidelines
RH+: Row-Hit-Optimized Scheduling for PIM-based LLM Inference
Optical Implementation of Equilibrium Propagation Using Spatial Photonic Ising Machines
GRAFT: Graphlet-Triggered Backdoor Attack on GNN-Based Hardware Security Systems
LLM-Guided Neural Architecture Search for Robust Co-Design of Physical Neural Networks
Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators
Feasibility of Time-Domain DNN-Based Speech Enhancement on Embedded FPGA for Hearing Aid
StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
Characterizing the Impact of NVFP4 Quantization for Low-Power Edge AI Deployment
Quantized AI Inference on Constrained Embedded Platforms for Small-Satellite Settings
A 65 nm Multi-Modal Bayesian Inference Engine with 16.3 fJ/Sample Calibration-Free GRNG for Risk-Aware At-Home Skin Lesion Screening
A 65-nm Privacy-Preserving Neuromorphic Encoder With 7.13-nJ Efficiency, 2.38-Mb/mm^2 Item-Memory Density, and Federated Learning Support
A 65 nm Trustworthy Hypoglycemia Forecasting Engine Achieving 11.3 nJ per Inference
ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips
SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing
Specifying Hardware Communication as Programs
A Fast Locality Simulator for GEMM Design-Space Exploration on Multi-Chiplet GPUs
Making Locality-aware GEMM Compatible with Page-Granularity Placement on Chiplet GPUs
BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics
Partitioned Tags, Shared Data: Reconciling Strict Cache Isolation with Write-Shared Coherence
MAC Hardware Implementation
QBugLM: An Agentic Benchmarking Framework for LLM-based Quantum Software Debugging
Multi-Segment Attention: Enabling Efficient KV-Cache Management for Faster Large Language Model Serving
Glass Box at Orbit: A Constitutional AI Verification Framework for Trustworthy Autonomous CubeSat Intelligence
MOSAIC: Efficient Mixture-of-Agent Scheduling via Adaptive Aggregation and Inference Concurrency
High Perfermance Snort Architecture Design Based on Network Application Processor
World Models: A Comprehensive Survey of Architectures, Methodologies, Reasoning Paradigms, and Applications
GaMi: Geometry-Agnostic Material Identification via Cross-Modal Subtractive Disentanglement
Benchmarking the ORCA PT-2 Boson Sampler using Minimum Dominating Set Problems
Accelerating NBTI Aging Evaluation via Physics-Aware Graph Attention Networks
Profiling cognitive offloading in LLM-mediated synthesis writing: Volume vs. content
Flexible Flows for Biological Sequence Design
Blockchain Infrastructure for Intelligent Cyber--Physical--Social Systems:Post-Quantum Security, Interoperability, and Trustworthy Data Economies in the Era of Embodied AI
Toward a Full-Stack Framework for Industrial Augmented Reality: Benefits, Risks, and Design Considerations for Dependable Deployment in Manufacturing
RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits
GoldenFloat: A Phi-Derived Static-Split Floating-Point Family from GF4 to GF256 with a Lucas-Exact Integer Identity
BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference
AttentionCap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction
ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
Programming Domain-Specific FPGA Hardblocks from HLS: An RTL Blackbox Approach
Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory
Silicon Photonics Testing: Design for Testability, Fault Detection, and Manufacturing Variation Analysis in Photonic Integrated Circuits
PALUTE: Processing-In-Memory Acceleration via Lookup Table for Edge LLM Inference
Sustainability and Artificial Intelligence: Necessary, Challenging, and Promising Intersections
NeuDW-CIM: a 65-nm 0.8-pJ/Sop Reconfigurable Neuromorphic Compute-in-Memory Macro with Nonlinear Dendrites and K-Winners
OpenOpt: An Open-Source SRAM Optimizer Based on Equivalent Circuit Model
SIFT: Selective-Index For Fast Compute of RAG Prefill by Exploiting Attention Invariance
Precomputed 1D-CNNs for Atrial Fibrillation Detection on Tiny Smart Sensor Systems
elasticAI.explorer: Towards a Unified End-to-End Framework for Hardware-Aware Neural Architecture Search
AgentRedBench: Dynamic Redteaming and Integration-Aware Defense for LLM Agents over SaaS Integrations
CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation
Fast Transformer Inference on ARM-Based HMPSoCs
P-Cast Precision in FP8 Attention: Sink-Induced Collapse and the Optimality of S=2^8
HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite
ВИДЫ КОМПЬЮТЕРНЫХ ВИРУСОВ: СПОСОБЫ ЗАЩИТЫ КОМПЬЮТЕРА ОТ ВИРУСОВ
РАЗРАБОТКА СИСТЕМЫ МОНИТОРИНГА СЕТИ
Перспективы развития производства компьютеров, электронных и оптических изделий в Южном федеральном округе в условиях экономических санкций
ПРИМЕНЕНИЕ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА ДЛЯ ОПТИМИЗАЦИИ ПРОЦЕССОВ ПРОИЗВОДСТВА В ПРОМЫШЛЕННОСТИ
Wave Focusing in Metamaterials: Tactile Displays Beyond the Diffraction Limit
FQA: A Full-Space Quantization-Driven Architecture for Hardware-Efficient Piecewise Approximation of Nonlinear Activation Functions
Microprogrammed CPU Design
From Roofline to Ruggedness: Decomposing and Smoothing the GEMM Performance Landscape
Night-Window Batching versus Carbon-Aware Scheduling for Clinical AI GPU Workloads
Branch-Aware Quantum Constant Propagation for Dynamic Quantum Circuits
Heterogeneous Mapping for Analog In-Memory Computing Accelerators: A Unified Workflow
AURA: Action-Gated Memory for Robot Policies at Constant VRAM
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Space-CIM: Enabling Compute-In-Memory Accelerators for Thermally-Constrained Space Platforms
ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
Modeling, Optimizing and Exploring Multi-Die FPGA Routing Architectures
Activation Concentration: Characterizing Column-Level Output Sparsity Across Diffusion Model Architectures
LP5X-PIM Sim: A High-Fidelity HW/SW Integrated Simulator for LPDDR5X-PIM
Linear Complexity Fermionic Simulation on Quantum Devices with Hardware Connectivity Constraints
Can AI Review Improve Paper Drafting? An Empirical Study on 20 Computer Architecture Submissions
Functional Interface Blocks for Neuromorphic Hardware: A Junction-Centered Framework
Speculating the Impacts of Mediated Social Touch Technology
ThermoPix: A High-Spatial-Resolution ElectronicPhotonic Temperature Sensor Array With Microsecond Row Readout
Expressibility, Noise, and Error Mitigation in VQE Ansatz Selection
Learning to Evaluate: Cost-Effective Model Evaluation on Unlabeled Data with Meta-Learning
Quantum-Adaptive KS($\varphi$): A Parameterized Three-Qubit Gate Family Embedding Toffoli with Measurement-Free Phase Kickback and Intrinsic Error Non-Amplification
Toward Secure Operation and Management (O&M) of Satellite Constellations: Efficiency, Resilience, and Reliability in a Network Perspective
The Energy Blind Spot: NVIDIA's Flagship Edge AI Hardware Cannot Support Process-Level Energy Attribution
CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
CLIPGen: A Chiplet Link IP Modeling and Generation Framework for 2.5D Architecture Exploration
HammerSim: A System-Level Tool to Model RowHammer
ACRONYM: Accelerated Approximate Nearest Neighbor Search in Memory for Dynamic Vector Databases
Q-FE: A Quantum-Native 6G Far-Edge Architecture Securing Industrial IoT Digital Twins via CSIDH-PQC and Asynchronous Federated Learning
SA-DTS: Semantic-Aware Digital Twin Synchronization over 6G Networks
SPARQLe: Sub-Precision Activation Representation for Quantized LLM Inference
Cassandra: Enabling Reasoning LLMs at Edge via Self-Speculative Decoding
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling
Hardware Description Languages
A Four-Tier Communication Architecture and Sim-to-Real Validation of a Graphical Open-Source Platform for Robotic Engineering Education
When NPUs Are Not Always Faster: A Stage-Level Analysis of Mobile LLM Inference
Advanced Processor Design
Invasive Tightly Coupled Processor Arrays
Observation, Not Prediction: Conversation-Level Disaggregated Scheduling for Agentic Serving
Implementation and Optimization of HQC Decoding on NPU-Integrated Devices
O-POPE: High-Frequency Pipelined Outer Product based GEMM acceleration with minimal buffering overhead
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
Federated Formal Verification: Cross-Backend Citation, Cross-Axis Convergence, and AI-Orchestrated Proof Dispatch for Production Systems
AgentRedBench: Dynamic Redteaming and Integration-Aware Defense for LLM Agents over SaaS Integrations
Towards Automated Discovery: A Review of Generative Models, Multimodal Learning and Closed-Loop Workflows in Inverse Materials Design
ClinEnv: An Interactive Multi-Stage Long Horizon EHR Environment for Agents
Memory-Bound but Not Bandwidth-Limited: The Physical AI Inference Gap in Batch-1 LLM Decode
A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
HE^2: A Communication-Light Heterogeneous Architecture for Efficient Fully Homomorphic Encryption
MixFP4: Enhancing NVFP4 with Adaptive FP4/INT4 Block Representations
Memristor-Based Spiking Neural Network Accelerator for Bio-inspired Interception Task
Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations
Predictive Software Scheduling as an Early-Warning Hint Layer for Optical Engine Thermal Drift in Heterogeneous SoIC Packaging
ACALSim: A Scalable Parallel Simulation Framework for High-Performance System Design Space Exploration
MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
NASiC: 3D NAND-based CAM-Selected Multibit CIM Architecture for Efficient On-Device Mixture-of-Experts LLM Inference
A generic wrapper architecture for multi-processor SoC cosimulation and design
XL-HD: Extended Learning in Hyperdimensional Computing via Deterministic Projections for In-Memory Accelerators
RouteScan: A Non-Intrusive Approach to Auditing MoE LLMs Safety via Expert Routing Telemetry
Architectural Limits of Cloud TPUs in Finite-Field Cryptography
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
μ-ORCA: Optimizing Acceleration for Microsecond-Scale Deep Neural Network Inference on ACAP
ROA-Based Subharmonic Injection Locking for Oscillator-Based Ising Machines
Synthesis and Optimization of Encoding Circuits for Fault-Tolerant Quantum Computation
Lightweight Cross-Device Sleep Tracking on the WeBe Wearable Platform
EnThM: Energy Theft Mitigation in Smart Grids using Hierarchical Verification of Metering Data
Grow-Prune-Freeze Networks: Adaptive & Continual Learning Technique for Olfactory Navigation
Decoupling Reentrancy Protection from Smart Contract Implementation Logic
Ring-LWE Public Key Encryption Processor
A Domain-Informed Multi-Objective Framework for EEG Channel Selection in Motor Imagery BCIs
The Rise of the Software-Defined Vehicle: Architectures, Enabling Technologies, and Future Opportunities
Side-Channel Threats and Protections
Constant Depth Threshold Circuits For Exhaustive Epistasis Detection
Design-Oriented Modeling of TSV Substrate Noise Coupling to Ring VCOs
Precomputed 1D-CNNs for Atrial Fibrillation Detection on Tiny Smart Sensor Systems
elasticAI.explorer: Towards a Unified End-to-End Framework for Hardware-Aware Neural Architecture Search
Compile-Time Simplification of Classically Controlled Operations in Dynamic Circuits
FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
Nonvolatile Charge-Domain Attention with HZO Ferroelectric Capacitors: A Simulation-Based Device-to-System Evaluation
Range, Not Precision: Block-Floating-Point Half-Precision FFT and SAR Imaging on Apple Silicon
A PROCESSOR-COPROCESSOR ARCHITECTURE FOR HIGH END VIDEO APPLICATIONS
Hands-on computer architecture
On-Demand Fault Tolerance on Massively Parallel Processor Arrays
Cooperative Robotics Reinforced by Collective Perception for Traffic Moderation
CPPL: A Circuit Prompt Programming Language
Decompose, Optimize, and Reconstruct: Very Large Constant Multiplication at Scale
Estimating Target Doppler in Unsynchronized Multistatic ISAC Deployments with Mobile Nodes
PauLIB: A High-Performance Library for Processing Pauli Strings
Beyond the Data Mesh Illusion: Designing Modern AI-augmented Lakehouses to Bridge the Gap Between Theory and Practice
Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory
Code size reduction by advanced near addressing modes
Posture Clip: Sit properly or I wont let you work
DiSC: Resolution-Scalable Acceleration of Diffusion Models by Exploiting Sparsity and Cached Token Reuse with Hash-based Distribution
Mutually Unbiased Bases for Variational Quantum Initialization: Basis-Union Optimality and Adaptive Family Search
Evaluating System-Level Fidelity with Peaked Random Circuits
The Evolution of Digital Twins from Reactive to Agentic Systems
PoisonCap: Efficient Hierarchical Temporal Safety for CHERI
Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generation
dSABRE: A SABRE-Style Router for Multi-Core Distributed Quantum Computers
LIDSA: Cognitive Arbitration for Signal-Free Autonomous Intersection Management
A Rigid Category of DNA Secondary Structures
A Hybrid Tucker-LSTM Tensor Network Model for SOC Prediction in Electric Vehicles
Embodied Neurocomputation: A Framework for Interfacing Biological Neural Cultures with Scaled Task-Driven Validation
Design of 5-Stage Hazard-Free Pipelined Architecture for RISC-V-Based Processor
Automatic De-Quantization of Quantum Programs Using Constant Propagation
Which Superconducting Qubit Model is Good Enough? From Effective Two-Level to Circuit-Based Hamiltonians for Pulse-Level Simulation
Classical State Preparation for Variational Quantum Algorithms via Reinforcement Learning
Cost-Effective Model Evaluation with Meta-Learning
Jurisdiction over Ubiquitous Copyright Infringements: Should Right-Holders Be Allowed to Sue at Home?
Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates
The Hidden Cost of Contextual Sycophancy: an AI Literacy Intervention in Human-AI Collaboration
DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems
UniSpike: Accelerating Spiking Neural Networks on Neuromorphic Systems via Eliminating Address Redundancy
DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
Hardware Design Space Exploration of a Selection of NIST Lightweight Cryptography Candidates
Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design
Search Your Block Floating Point Scales!
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
A detailed algorithmic study on a reuse-aware, near memory, all-digital Ising machine
GenAI-Driven Approach to RISC-V Supply Chain Exploration
TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces
VeriCache: Turning Lossy KV Cache into Lossless LLM Inference
TuniQ: Autotuning Compilation Passes for Quantum Workloads at Scale for Effectiveness and Efficiency
Performance of QUBO-Formulated MIMO Detection Under Hardware Precision Constraints
A Fast and Energy-Efficient Latch-Based Memristive Analog Content-Addressable Memory
When Noisy Quantum Order Finding Remains Recoverable for Shor's Algorithm
Performance Gains in Quantum SAT Solvers Using ESOP Encoding
BIDO: A Biometric Identity Online Authentication Framework
Quantum Genetic Optimization for Negative Selection Algorithms in Anomaly Detection
Whole-Blood Boundary Analysis of BioFET-Based ctDNA Detection for Intravascular Sensing in Intrabody Nanonetworks
Stencil Computations on Tenstorrent Wormhole
Per-Phase Fidelity Attribution for Quantum Compilers using HBR Decomposition
LCGuard: Latent Communication Guard for Safe KV Sharing in Multi-Agent Systems
Non-Monotonic Latency in Apple MPS Decoding: KV Cache Interactions and Execution Regimes
31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding
CompPow: A Case for Component-level GPU Power Management
Emerging memory technologies at room/cryogenic temperature
NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing
ORBIS: Output-Guided Token Reduction with Distribution-Aware Matching for Video Diffusion Acceleration
Coarse-granularity 3D Processor Design
An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture
Multiprocessor and Many-Core Protections
Low Resource-Cost Depthwise Separable Convolutional Co-Processor Architecture : Embedded Co-Processor Design
ELSA: An ELastic SNN Inference Architecture for Efficient Neuromorphic Computing
Towards transistor-based quantum computing
Cloud-Native Operation of Roadside Infrastructure Enabling Demand-Driven Collective Perception via V2X
Supporting Dynamic Control-Flow Execution for Runtime Reconfigurable Processors
Processor and Instruction-Set Architectures
Execution Envelopes: A Shared Admission Contract for Backend AI Execution Requests
Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation
A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
Low-Complexity Beamspace Channel Denoiser for mmWave Massive MIMO with Low-Resolution ADCs
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
Inverse Design of Metasurface based Absorbers using Physics Guided Conditional Diffusion Models
Verification Challenges in Configurable Processor Design with ASIP Meister
Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models
Quantum Annealing: Optimisation, Sampling, and Many-Body Dynamics
Genetic Information as a "Chord" of Chemical Oscillations: Emergence of Catalyst-RNA Systems Driven by Superposed Rhythms
A3D: Agentic AI flow for autonomous Accelerator Design
Hardware Root of Trust
A Simple Computer: Hardware Design
Post-Moore Technologies for Plasma Simulation: A Community Roadmap
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs
FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors
An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration
Vector and Multiple-Processor Machines
Processor and Instruction-Set Architectures
Dual-Execution Processor Architecture for Embedded Computing
Adaptive Clifford+T Decomposition of Large Toffoli Gates with One Clean Ancilla
Efficient Implementation of an Adaptive Transformer Accelerator for Massive MIMO Outdoor Localization
Memristor Technologies for Dynamic Vision Sensors: A Critical Assessment and Research Roadmap
■ HARDWARE ARCHITECTURE
IBM AS/400 processor architecture and design methodology
Power Efficient Processor Architecture and The Cell Processor
A Case Study: Formal Verification of Processor Critical Properties
An Efficient Hardware Architecture Design of EEMD Processor for Electrocardiography Signal
Teaching Computer Architecture through an Integrated Top-Down RISC-V Processor Design Approach
Introduction
Abc's Of Processor Design: Introductory Computer Architecture Using The Lis 4
Runtime Calibration as State-Trajectory Feedback Control in Quantum-Classical Workflows
Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations
Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
Enhancing Instruction Prefetching via Cache and TLB Management
Hardware Design Using Verilog
MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
LLM-Driven Design Space Exploration of FPGA-based Accelerators
A virtually connected probabilistic computer as a solver for higher-order, densely connected, or reconfigurable combinatorial optimisation problems
XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture
Analysis of Hardware Sorting Units in Processor Design
Principles of Secure Processor Architecture Design
Processor Design Case Studies
Vector and Multiple-Processor Machines
Principles of Secure Processor Architecture Design
Processor Design Case Studies
An Integrated PPG and ECG Signal Processing Hardware Architecture Design of EEMD Processor
Processor and Instruction Set Architectures
Hardware Cost Estimation for Application-Specific Processor Design
RFAmpDesigner: A Self-Evolving Multi-Agent LLM Framework for Automated Radio Frequency Amplifier Design
Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring
Towards an End-To-End System for Real-Time Gesture Recognition from Surface Vibrations
ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits
Establishing Robust Retinal Eye Tracking: A Weakly Supervised Algorithmic Framework
Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization
A Hybrid Classical-Quantum Annealing Algorithm for the TSP
SCOPE: Siamese Contrastive Operon Pair Embeddings for Functional Sequence Representation and Classification
Basic Computer Security Concepts
A model-year architecture approach to hardware reuse in digital signal processor system design
Evolving Layer-Specific Scalar Functions for Hardware-Aware Transformer Adaptation
Time Domain Near Memory Computing Engine
A Hardware-Aware, Per-Layer Methodology for Post-Training Quantization of Large Language Models
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
Fine-granularity 3D Processor Design
Hardware Description Languages
General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies
Session 2B: Application Specific Memory and Processor Architecture Design Techniques
A generic wrapper architecture for multi-processor SoC cosimulation and design
Conclusions and Future Work
Hardware / Software Co-design using LEON3 Processor: AES as Case Study
Hardware: The ERRIC Architecture
Wireless sensor nodes processor architecture and design
Improved Processor Design Project Testing
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware

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